1. Field of the Invention
The invention relates to a method for operating a comparator and a pre-amplifier of an integrated circuit, which pre-amplifier is connected in series to the comparator, according to the precharacterising part of claim 1, as well as to an integrated circuit arrangement comprising a comparator and a pre-amplifier which is connected in series to the comparator, according to the precharacterising part of claim 9.
2. Description of the Prior Art
Such a method and such a circuit arrangement is for example known from xe2x80x9cRazavi et al, IEEE Journal of Solid-state Circuits, vol. 27, no. 12, December 1992, pp. 1916-1926xe2x80x9d. FIG. 1 of said article diagrammatically shows a comparator with a pre-amplifier connected in series. FIGS. 5 and 6 of said article show embodiments of a pre-amplifier which can be operated with clock pulses, and of a comparator (latch) which can be operated with clock pulses. By means of suitably selected periodical clock pulse signals for controlling the pre-amplifier and the comparator, this arrangement makes it possible, at periodical decision points, to compare the signals which are present at the input of the arrangement.
From xe2x80x9cNagaraj et al, IEEE Journal of Solid-state Circuits, vol. 35, no. 12, December 2000, pp. 1760-1768xe2x80x9d, a similar circuit arrangement is known. FIG. 6 of said article shows the arrangement in an ADC, wherein two pre-amplifier stages are connected in series to individual comparators (latches). FIGS. 8 and 11 of this article show the design of the first pre-amplifier stage and the periodical signal gradients of the pre-amplifier stages which are operated with clock pulses.
From xe2x80x9cDavid Johns, Ken Martin, Analog Integrated Circuit Design, J. Wiley and Sons, 1997, pp. 316-331 (compare FIG. 7.13 of said article), it is know to connect a pre-amplifier in series to a comparator.
FIG. 1 shows an arrangement, designed in the known way, comprising a comparator 10 and a pre-amplifier 20 which has been connected in series to the comparator 10 so as to improve the resolution. As is also shown in FIG. 1, it is also possible to connect several pre-amplifiers in series to the comparator 10.
By being controlled with a periodical clock pulse signal CLK, the comparator 10 is operated so as to compare comparator input signals at periodical decision points, wherein said comparator input signals are provided to the comparator 10 by the pre-amplifier 20 in the form of output signals OUT+ and OUTxe2x88x92. At its output, the comparator 10 provides a comparator output signal which corresponds to the comparison result, namely a binary signal COUT and a signal COUT* which is inverse to the former. The pre-amplifier 20 (or the multiple number of pre-amplifiers) is/are operated by being controlled with a further periodical clock pulse signal (RST) (reset signal) so as, in amplification phases which precede the decision points, to amplify a signal which has been input to the pre-amplifier (in this instance the difference between two signals IN+ and INxe2x88x92) and to provide the amplified signal as a comparator input signal (difference between signals OUT+ and OUTxe2x88x92), and so as, in reset phases which precede the amplification phases, to reset amplification to a minimum value (reset). This reset function prevents hysteresis effects as well as dependence of the output signals OUT+, OUTxe2x88x92 on the past history of these signals in preceding clock pulse cycles. Preferably, the minimum value of amplification is significantly less than 1.
FIG. 2 shows an exemplary embodiment of the pre-amplifier 20. A pre-amplifier designed in this way is for example known from the above-mentioned IEEE article (Nagaraj et al) and is shown in FIG. 8 of said article. The pre-amplifier comprises a transconductance stage which is formed from a differential pair of two FETs Q1, Q2, as well as a resistive load in the form of ohmic resistors R1, R2, arranged in series to the FETs Q1, Q2. As an alternative, the resistive load could for example also be formed by MOS diodes.
The differential input signals IN+, INxe2x88x92 are fed to the control-current terminals of the FETs Q1, Q2, so that on nodes between these FETs and the resistors R1, R2, the amplified signal is provided as the difference between two signals OUT+, OUTxe2x88x92, wherein, as is well known, amplification is greater the greater the transconductance in the transconductance stage, and the greater the resistive load.
A time constant (RC constant) is decisive for the dynamic behaviour of the pre-amplifier 20, with said time constant being the product from resistive load and capacities. Such capacities, above all parasitic capacities, are unavoidable at the output of the pre-amplifier 20 itself and as a result of the input capacity of the subsequent stage (comparator or further pre-amplifier).
The reset function of the pre-amplifier 20, which is clock pulsed with the reset signal RST, takes place by means of a further FET Q3, which is arranged between pre-amplifier output lines which are intended for providing the amplified signal, with said further FET Q3 being operated as a switch, in that the binary reset signal RST is fed to the control-current terminal of said FET Q3. During a reset phase the FET Q3 is switched on so that the pre-amplifier output lines are short-circuited by way of a relatively small source-drain resistor. As a result of this, amplification is reset to a minimum value (approaching zero), while the time constant also becomes small, so that consequently the output signal OUT+xe2x88x92OUTxe2x88x92 quickly drops to values near zero. This reset function prevents hysteresis effects and during the reset phase clears any signal excursion which may still be present at the output so that in the next clock pulse cycle the output signal does not depend on the past history.
During an amplification phase which immediately follows the reset phase, the output signal of the pre-amplifier 20 should follow the input signal (which is variable in time). At the end of the amplification phase, i.e. at the decision point of the comparator 10, the output signal has to be at least on the same side of the decision threshold as the input signal so as to ensure a reliable comparison function. In many cases of application, the characteristics of the input signal are such that, from a starting value which does not correlate to the final value, or only faintly correlates to the final value (e.g. along an exponential transient response curve), said input signal aims to reach the final value. This case occurs in particular at the output of an SC (switched-capacitor) circuit, for example in the context of quantisers in delta-sigma modulators. The case where the input signal starts with considerable excursion on one side of the decision threshold and changes to the other side only towards the end of the amplification phase constitutes the most difficult case for designing the amplifier time constant. This case is shown in FIG. 3. The solid curve shows the gradient over time of the input signal. If the pre-amplifier 20 is designed for a short time constant and thus high speed, approximately the output signal gradient shown by a dot-dash line in FIG. 3 results. If the pre-amplifier 20 is designed for a longer time constant and thus a lower speed, approximately the output signal gradient shown by a dashed line in FIG. 3 results. In the first case, the final value of the output signal is on the same side as the decision threshold (dotted line), whereas in the second case, the output signal of the pre-amplifier 20 cannot follow the input signal fast enough and is still located on the other side of the decision threshold. If this second case is to be avoided, the time constant will have to be shortened. This can easily be brought about by reducing the resistive load. In practical application it is rarely possible to reduce the capacities which are decisive for the time constant. As a rule, these capacities result as parasitic capacities due to less than perfect matching of circuit components.
In order to maintain unchanged the amplification which is to be achieved when the resistive load is reduced, it is however subsequently necessary to increase the transconductance of the transconductance stage. In the pre-amplifier 20 shown in FIG. 2 this means an increase of the FET bias current, i.e. of the current which flows without an input signal through the FETs Q1 and Q2. As is well known, the magnitude of the transconductance of a FET directly depends on the magnitude of this bias current.
Thus, if the pre-amplifier 20 is designed for an input signal which varies over time, which aims to reach the final value only during the amplification phase, wherein it should be ensured that the output signal follows the input signal at adequate speed, then the current consumption of the pre-amplifier must be clearly increased when compared to the case of a constant input signal.
From xe2x80x9cOehler, F. et al, A 3.6 Gigasample/s 5 bit Analog to Digital Converter using 0.3 xcexcm AIGaAs-HEMT Technology, in IEEE, GaAs IC Symposium 1993, pp. 163-166xe2x80x9d it is known to connect in series a continuously operated pre-amplifier to a comparator which is operated with clock pulses.
U.S. Pat. No. 4,241,455 describes a circuit arrangement for receiving and processing signals which were input to the circuit by way of an optical detector. These are digital data signals which are processed by the circuit arrangement by means of a number of processing stages, with comparators being used at the end of said processing stages. A pre-amplifier of this known circuit arrangement is in continuous operation.
It is an object of the present invention to eliminate the disadvantages stated above, and in particular to provide a circuit arrangement and a method of the type described in the introduction, in which the pre-amplifier, even with low current consumption, at the decision point of the comparator provides output signals which are suitable for making a reliable decision.
This object is met by a method according to claim 1, and a circuit arrangement according to claim 9. The dependent claims relate to advantageous improvements of the invention.
It is essential to the invention that amplification during a rise phase within the amplification phase rises uniformly and gradually from the minimum value to a maximum value. In most application cases this rise phase preferably takes up at least 10%, more preferably at least 50% of the amplification phase.
The function of the invention can be mathematically explained by means of a linear model of the pre-amplifier, as follows. The final value (at the end of the amplification phase) of the output signal can be obtained from a convolution of the input signal with the pulse response of the pre-amplifier. The slower the amplifier, the greater the contribution which the fractions of the input signals at the beginning of the amplifier phase make to the final value of the output signal. The invention is based on the fundamental idea of influencing the form of the pulse response (weight function) by providing amplification which is variable over time. By means of a suitable selection of the gradient over time of the size of the resistive load, the form of the pulse response can be changed over an extended region. By providing a rise phase in which amplification rises, it is possible to more or less xe2x80x9cdecouplexe2x80x9d the objectives of providing a reliable output signal at the end of the amplification phase while achieving low current consumption of the pre-amplifier (i.e. objectives which are competing in the state of the art), and to provide a pre-amplifier with lower current consumption in which the starting value (at the beginning of the amplification phase) of the input signal makes a small contribution to the final value of the output signal, whereas input signals at the end of the amplification phase make a comparatively large contribution to the output signal at the decision point.